Monday, February 25, 2013

Toshiba Announces Low Power Innovations, Presents them at ISSCC

Business Wire: Toshiba announces a CMOS sensor technology with a small area and low power pixel readout circuits. A sample sensor embedded with the readout circuits shows double the performance of a conventional one (compared using FOM = power x noise / (pixels x frame rate)). Toshiba presented this development at ISSCC 2013 in San Francisco, CA on Feb. 20.

Toshiba has developed three key technologies to overcome these challenges:
  1. Column CDS circuits primarily made up of area-efficient PMOS capacitors. The area of the CDS circuits is reduced to about half that of conventional circuits.
  2. In the readout circuits, a level shift function is simultaneously achieved by a capacitive coupling through the PMOS capacitors, allowing adjustment of the signal dynamic range between the column CDS circuits and the PGA and the ADC. This achieves low power and low voltage implementation of the PGA and ADC, reducing their power consumption by 40%.
  3. Implementation of a low power switching procedure in the ADC suited to processing the pixel signals of CMOS image sensors. This reduces the switching power consumption of the ADC by 80%.
Toshiba has integrated the three technologies in a sample sensor and confirmed that they double the overall performance of the sensor core. The company now plans to use these innovations in CMOS sensors for low cost mobile phones and medical cameras in fiscal year 2013.

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